The invention relates to a system for measuring the thickness of a semiconductor wafer over a region of the wafer.
Using current semiconductor device fabrication technology, integrated circuit manufacturers are able to produce hundreds of circuit chips from a single large wafer. Each circuit chip may in turn contain millions of devices. The devices in the circuits are typically fabricated one layer at a time, each layer associated with a different part of the underlying semiconductor device structures. For example, there may be a diffusion stage during which electrically isolated islands are created in the underlying semiconductor wafer. Then there are subsequent diffusion stages in which devices are fabricated in those islands. Near the end of the fabrication process there at least one metalization layer is formed on the wafer interconnecting all of the devices on the circuit. The stages of the fabrication process are represented by a series of masks, at least one mask for each stage of the process. Thus, there will be a mask for the isolation diffusion, masks for each of the subsequent diffusions, and at least one mask for the metalization layer.
The sequence of steps used to fabricate the various layers of the integrated circuit on the wafer are similar. In a diffusion-based fabrication process, for example, the fabrication of an individual layer might involve the following steps. First, a passivation layer is grown or deposited on the surface of the wafer. The passivation layer prevents diffusion of dopants into the underlying wafer during a subsequent diffusion step. Windows are then opened up through the passivation layer to identify those areas in which it is desired to diffuse a dopant into wafer. This is done by first depositing a photoresist (or some material sensitive to the particular energy source that is used, e.g. X-rays) on top of the passivation layer. Then, a mask having a pattern of the regions in which diffusion is not desired is imaged onto the photoresist thereby exposing the photoresist in those selected regions. The exposed photoresist is developed and the unexposed regions are dissolved away, thereby exposing the passivation layer. Next, the wafer is placed in an etchant solution. The etchant etches away the passivation layer only in those regions that are not protected by the photoresist. After the etching step is complete, the developed photoresist is removed and the wafer is placed in a diffusion furnace where dopant is diffused into the wafer in the selected regions.
Because of the large size and the complexity of the circuits now being fabricated, the masks that are used in the photolithographic process represent only a single circuit. To create many circuits on a single wafer, the photolithographic equipment uses a step and repeat technique to print many images of that one circuit over the surface of the wafer, one at a time. For each step of the step and repeat process, the equipment focuses the mask onto a different area of the wafer. This is accomplished by leveling the wafer to the focal plane of the stepper system so that the entire image of the circuit is properly in focus over the relevant region of the wafer. The optics which perform the imaging are typically only micrometers above the surface of the wafer.
This entire process depends on sophisticated, high resolution photolithographic equipment and starting material (i.e., wafers) of very high quality. If the wafers are not sufficiently flat, the photolithographic equipment will not be able to properly focus the image of the circuit onto the desired location of the wafer or, during the process of leveling the wafer to the focal plane of the stepper system, the wafer will physically strike the equipment. In either event the consequences are unacceptable.
Thus, it is very desirable to identify before the wafer is placed in the photolithographic equipment those wafers that do not meet the required level of flatness. Since the uniformity of wafer thickness is a measure of wafer flatness, some manufacturers use wafer thickness measuring instruments to identify wafers which are not within specification on flatness. One instrument for that purpose uses two capacitive probes. One capacitive probe is positioned on one side of the wafer and the second capacitive probe is positioned in alignment and at a fixed distance from the first probe but on the opposite side of the wafer. The measured capacitance is an indication of the distance of both probes from the two surfaces of the wafer. Thus, since the separation of the probes remains constant, any changes in the measured capacitance are an indication of changes in the thickness of the wafer.
The problem with such systems, however, is that resolution is not as great as desired. The probe sizes, for example, may be on the order of 4 mm square but the desired resolution is greater than that. Indeed, even if the resolution of the probes were to improve, which is likely, it would always be desirable to obtain measurements at a resolution which exceeded that of the equipment available.
The described embodiment utilizes the capacitive probes to generate the thickness measurements. Then, a programmed computer using techniques to be described herein processes that data to enhance its resolution. The technique utilizes blur functions and tensor techniques to enhance the resolution of the thickness measurements.